The IP cores are optimised for use in FPGA but can be adapted and licensed for use in ASIC.

easyIRT unleashes the full power of the RT Communication Core.

The Profinet IRT IP core, developed by InES, can easily be combined with other IP cores to build entire System on Chip (SoC) solutions. Featuring a complete IEEE 1588 PTP implementation in hardware, this core can uphold standard cycle times of 31.25us without batting the proverbial eye. Using a 400MHz timestamp synchronisation accuracy of 60ns over 20 nodes can be reached.

The ability of PROFINET to ensure bandwidth efficiency is due to clock distribution and synchronisation as provided by IEEE 1588 PTP. IEEE 1588 represents a discrete digital control algorithm acting on a continuous analog transfer function acting on the system quartz. The rate of change of synchronisation between two nodes is directly dependent on the rate of change of the slave clock, more precisely the relative change of the master and slave clock, which is also directly dependent to the rate of change of external influences (acceleration, temperature, pressure) on the system quartz. For high precision synchronisation, effectively a small error rate, the sampling time must be much smaller than this rate. The sampling time however is dependent on the cycle time of the communication system. An optimal cycle time of 1ms can only be upheld in a communication cycle time of 2 ms by multiple transmission of SYNC frames within that cycle. For many implementations a standard software implementation of IEEE 1588 is sufficient.

In high performance systems with low cycle times (>125ns) it can be recommendable to send a SYNC frame every cycle-time. The issue here is that with especially fast cycle times the system processor may be absorbed with servicing the PTP algorithm - in order to service the application a higher-power processor may be needed thus increasing system cost.

A perfect remedy to this situation is to implement the PTP algorithm in “portable hardware”, specifically VHDL code. The incoming SYNC frames and the resultant DELAY REQ/RES frames may be automatically processed and the system clock synchronised without any processing required from the system processor.

The InES easyPTP solution is a 100% portable VHDL solution for implementing a PTP stack in either an ASIC or in a FPGA.

The precision of synchronisation is also (dramatically) dependent on the sampling clock of the time-stamps inserted into the SYNC and DELAY frames. With a standard sampling frequency of 50MHz, a typical FPGA internal clocking rate, a synchronisation precision over 4 nodes of 50ns is easily achieved.

InES has been a PROFINET International Competence Center and a regular contributor to the PICC conferences and exhibitor at fairs since 2003. InES, with its partners, offers trainings, consulting and technical support for PROFINET developers and manufacturers.